Forming and operating memory devices that utilize correlated electron material (CEM)

ABSTRACT

Subject matter disclosed herein may relate to fabrication of correlated electron materials (CEMs) devices used, for example, to read from a resistive memory element or to write to a resistive memory element. In embodiments, by limiting current flow through a CEM device, the CEM device may operate in the absence of Mott and/or Mott-like transitions in a way that brings about symmetrical diode-like operation of the CEM device.

RELATED APPLICATIONS

This application is a continuation of U.S. patent application Ser. No.15/610,288 entitled “FORMING AND OPERATING MEMORY DEVICES THAT UTILIZECORRELATED ELECTRON MATERIAL (CEM),” filed May 31, 2017, and isincorporated herein by reference in its entirety.

BACKGROUND Field

This disclosure relates to devices formed from correlated electronmaterials (CEMs), and may relate, more particularly, to approachestoward forming and operating memory devices coupled to CEM devices.

Information

Integrated circuit devices, such as electronic switching devices, forexample, may be found in a wide range of electronic device types. Forexample, memory and/or logic devices may incorporate electronic switchessuitable for use in computers, digital cameras, smart phones, tabletdevices, personal digital assistants, and so forth. Factors that relateto electronic switching devices, which may be of interest to a designerin considering whether an electronic switching device is suitable for aparticular application, may include physical size, storage density,operating voltages, impedance ranges, and/or power consumption, forexample. Other factors that may be of interest to designers may include,for example, cost of manufacture, ease of manufacture, scalability,and/or reliability. Moreover, there appears to be an ever-increasingneed for memory and/or logic devices that exhibit characteristics oflower power and/or higher speed. A need for lower power and/or higherspeed devices may involve a number of device types, which may, forexample, include devices fabricated, for example, at the front end ofline (FEOL) or at the back end of line (BEOL) of a wafer fabricationprocess.

BRIEF DESCRIPTION OF THE DRAWINGS

Claimed subject matter is particularly pointed out and distinctlyclaimed in the concluding portion of the specification. However, both asto organization and/or method of operation, together with objects,features, and/or advantages thereof, it may best be understood byreference to the following detailed description if read with theaccompanying drawings in which:

FIG. 1A is a graphical representation of an impedance profile of adevice formed from a CEM according to an embodiment;

FIG. 1B is an illustration of an embodiment of a CEM device and aschematic diagram of an equivalent circuit of the CEM device;

FIG. 2 is a graphical representation showing additional details of avoltage versus current profile of a device formed from a CEM accordingto an embodiment;

FIG. 3 is a graphical representation of an impedance profile of a CEMdevice operating as a diode and comprising at least partially symmetricoperation with respect to impedance of the CEM device, according to anembodiment;

FIG. 4 is a graphical representation of a voltage versus current profileof a resistive memory element according to an embodiment;

FIG. 5 is a graphical representation of an impedance profile of acompound device comprising a CEM device operating as a diode, coupled inseries with a resistive memory element according to an embodiment;

FIG. 6A is a graphical representation of an operating envelope, withrespect to voltage versus current, of a compound device according to anembodiment;

FIG. 6B is a schematic of a compound device comprising a CEM devicecoupled in series with a resistive memory element;

FIG. 7A is a schematic diagram showing an arrangement of compounddevices, such as those illustrated in FIG. 6B according to anembodiment;

FIG. 7B is a schematic diagram showing an arrangement of stackedcompound devices, such as the compound devices illustrated in FIG. 7A,according to an embodiment;

FIG. 8 is an illustration of a resistive memory element implemented onor over a CEM device at a back-end-of-line of a wafer fabricationprocess according to an embodiment; and

FIGS. 9-10 are flowcharts for methods of operating memory devices usinga CEM according to embodiments.

Reference is made in the following detailed description to accompanyingdrawings, which form a part hereof, wherein like numerals may designatelike parts throughout that are corresponding and/or analogous. It willbe appreciated that the figures have not necessarily been drawn toscale, such as for simplicity and/or clarity of illustration. Forexample, dimensions of some aspects may be exaggerated relative toothers. Further, it is to be understood that other embodiments may beutilized. Furthermore, structural and/or other changes may be madewithout departing from claimed subject matter. References throughoutthis specification to “claimed subject matter” refer to subject matterintended to be covered by one or more claims, or any portion thereof,and are not necessarily intended to refer to a complete claim set, to aparticular combination of claim sets (e.g., method claims, apparatusclaims, etc.), or to a particular claim. It should also be noted thatdirections and/or references, for example, such as up, down, top,bottom, and so on, may be used to facilitate discussion of drawings andare not intended to restrict application of claimed subject matter.Therefore, the following detailed description is not to be taken tolimit claimed subject matter and/or equivalents.

DETAILED DESCRIPTION

References throughout this specification to one implementation, animplementation, one embodiment, an embodiment, and/or the like meansthat a particular feature, structure, characteristic, and/or the likedescribed in relation to a particular implementation and/or embodimentis included in at least one implementation and/or embodiment of claimedsubject matter. Thus, appearances of such phrases, for example, invarious places throughout this specification are not necessarilyintended to refer to the same implementation and/or embodiment or to anyone particular implementation and/or embodiment. Furthermore, it is tobe understood that particular features, structures, characteristics,and/or the like described are capable of being combined in various waysin one or more implementations and/or embodiments and, therefore, arewithin intended claim scope. In general, of course, as has been the casefor the specification of a patent application, these and other issueshave a potential to vary in a particular context of usage. In otherwords, throughout the disclosure, particular context of descriptionand/or usage provides helpful guidance regarding reasonable inferencesto be drawn; however, likewise, “in this context” in general withoutfurther qualification refers to the context of the present disclosure.

Particular aspects of the present disclosure describe methods and/orprocesses for preparing, fabricating, and/or operating CEM devicesand/or other circuit elements, such as may be utilized to form a memoryelement comprising a CEM, for example, in a series arrangement with aresistive memory element. CEMs, which may be utilized in theconstruction memory system comprising CEM devices, for example, may alsocomprise a wide range of other electronic circuit types, such as, forexample, memory access devices, memory controllers, memory arrays,filter circuits, data converters, optical instruments, phase locked loopcircuits, microwave and millimeter wave components, and so forth,although claimed subject matter is not limited in scope in theserespects. In this context, a CEM device, for example, may exhibit asubstantially rapid conductor-to-insulator transition, which may bebrought about by electron correlations rather than solid statestructural phase changes, such as in response to a change from acrystalline to an amorphous state, for example, in a phase change memorydevice or, in another example, formation of filaments in phase changememory (PCM) devices. In one aspect, a substantially rapidconductor-to-insulator transition in a CEM device may be responsive to aquantum mechanical phenomenon, in contrast to melting/solidification orfilament formation, for example, in phase change memory devices. Suchquantum mechanical transitions between relatively conductive andrelatively insulative states, and/or between first and second impedancestates, for example, in a CEM device may be understood in any one ofseveral aspects. As used herein, the terms “relatively conductivestate,” “relatively lower impedance state,” and/or “metal state” may beinterchangeable, and/or may, at times, be referred to as a “relativelyconductive/lower impedance state.” Similarly, the terms “relativelyinsulative state” and “relatively higher impedance state” may be usedinterchangeably herein, and/or may, at times, be referred to as arelatively “insulative/higher impedance state.”

In an aspect, a quantum mechanical transition of a correlated electronmaterial between a relatively insulative/higher impedance state and arelatively conductive/lower impedance state, wherein the relativelyconductive/lower impedance state is substantially dissimilar from theinsulated/higher impedance state, may be understood in terms of a Motttransition. In accordance with a Mott transition, a material maytransition (e.g., turn-on) from a relatively insulative/higher impedancestate to a relatively conductive/lower impedance state. The Mottcriteria may be defined by (n_(c))^(1/3)a≈0.26, wherein n_(c) denotes aconcentration of electrons, and wherein “a” denotes the Bohr radius. Ifa threshold carrier concentration is achieved, such that the Mottcriteria is met, the Mott transition is believed to occur. Thus, in thiscontext, a “Mott transition” may comprise a transition of the state of aCEM from a relatively higher resistance/higher capacitance state (e.g.,an insulative/higher impedance state) to a relatively lowerresistance/lower capacitance state (e.g., a conductive/lower impedancestate) that is substantially dissimilar from the higherresistance/higher capacitance state. Likewise, in this context, a“Mott-like transition” may comprise a transition of the state of a CEMchanging from a relatively lower resistance/lower capacitance state(e.g., a conductive/lower impedance state) to a relatively higherresistance/higher capacitance state (e.g., an insulative/higherimpedance state). Accordingly, in this context, a “Mott or Mott-liketransition” occurring in a device, as referred to herein, means anabrupt change in localization of electrons, which affects an impedanceof the device. This may include, for example, conditions in a devicegiving rise to a set operation to place the device in a low impedance orconductive state or giving rise to a reset operation to place the devicein a high impedance or insulative state as described above.

Hence, a Mott transition may be brought about if carriers, such aselectrons, for example, are localized so as to give rise to a strongcoulomb interaction between the carriers. Such strong coulombinteraction is believed to split the bands of the CEM to bring about arelatively insulative (relatively higher impedance) state. If electronsare no longer localized, a weak coulomb interaction may dominate, whichmay give rise to a removal of band splitting, which may, in turn, bringabout a metal (conductive) band (relatively lower impedance state) thatis substantially dissimilar from the relatively higher impedance state.

Further, in an embodiment, a transition from a relativelyinsulative/higher impedance state to a substantially dissimilar andrelatively conductive/lower impedance state may bring about a change incapacitance in addition to a change in resistance. For example, a CEMdevice may exhibit a variable resistance together with a property ofvariable capacitance. In other words, impedance characteristics of a CEMdevice may include both resistive and capacitive components. Forexample, in a metal state, a CEM device may comprise a relatively lowelectric field that may approach zero, and therefore may exhibit asubstantially low capacitance, which may likewise approach zero.

Similarly, in a relatively insulative/higher impedance state, which maybe brought about by a higher density of bound or correlated electrons,an external electric field may be capable of penetrating the CEM and,therefore, the CEM may comprise higher capacitance based, at least inpart, on additional charges stored within the CEM. Thus, for example, atransition from a relatively insulative/higher impedance state to asubstantially dissimilar and relatively conductive/lower impedance statein a CEM device may result in changes in both resistance andcapacitance, at least in particular embodiments. Such a transition maybring about additional measurable phenomena, and claimed subject matteris not limited in this respect.

In an embodiment, a device formed from a CEM may comprise switching ofimpedance states responsive to a Mott or Mott-like transition in amajority of the volume of the CEM comprising a CEM-based device. In anembodiment, a CEM device may form a “bulk switch.” As used herein, theterm “bulk switch” refers to at least a majority volume of a CEMswitching a device's impedance state, such as in response to a Mott orMott-like transition. For example, in an embodiment, substantially allCEM of a device may switch from a relatively insulative/higher impedancestate to a relatively conductive/lower impedance state (Mott transition)or from a relatively conductive/lower impedance state to a relativelyinsulative/higher impedance state (Mott-like transition).

In implementations, a CEM device may comprise one or more “d-block”elements from of the periodic table of the elements, such as transitionmetals, transition metal compounds, one or more transition metal oxides(TMOs), for example. CEM devices may also be implemented utilizing oneor more “f-block” elements of the periodic table of the elements, suchas rare earth elements, oxides of rare earth elements, oxides comprisingone or more rare earth transitional metals, perovskites, yttrium, and/orytterbium, or any other compounds comprising metals from the lanthanideor actinide series of the periodic table of the elements, for example,and claimed subject matter is not limited in scope in this respect.Accordingly, in embodiments, a CEM device may comprise oxides of one ormore d-block elements and/or oxides of one or more f-block elements,having an atomic concentration of at least 85.0%, for example, with theremaining portion of the CEM device comprising a dopant such as, forexample, carbon or nitrogen. Thus, in this context, as the term is usedherein, a d-block element means an element comprising Scandium (Sc),titanium (Ti), vanadium (V), chromium (Cr), manganese (Mn), iron (Fe),cobalt (Co), nickel (Ni), copper (Cu), zinc (Zn), yttrium (Y), zirconium(Zr), niobium (Nb), molybdenum (Mo), technetium (Tc), ruthenium (Ru),rhodium (Rh), palladium (Pd), silver (Ag), cadmium (Cd), hafnium (Hf),tantalum (Ta), tungsten (W), rhenium (Re), osmium (Os), iridium (Ir),platinum (Pt), gold (Au), mercury (Hg), rutherfordium (Rf), dubnium(Db), seaborgium (Sg), bohrium (Bh), hassium (Hs), meitnerium (Mt),darmstadtium (Ds), roentgenium (Rg) or copernicium (Cn), or anycombination thereof. Also in this context, a CEM device formed from orcomprising an “f-block” element of the periodic table of the elementsmeans a CEM device comprising a metal or metal oxide from f-block of theperiodic table of the elements, which includes lanthanum (La), cerium(Ce), praseodymium (Pr), neodymium (Nd), promethium (Pm), samarium (Sm),europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), holmium(Ho), erbium (Er), thulium (Tm), ytterbium (Yb), lutetium (Lu), actinium(Ac), thorium (Th), protactinium (Pa), uranium (U), neptunium (Np),plutonium (Pu), americium (Am), berkelium (Bk), californium (Cf),einsteinium (Es), fermium (Fm), mendelevium (Md), nobelium (No) orlawrencium (Lr), or any combination thereof.

However, in particular embodiments, a Mott transition, indicating anabrupt change from a relatively higher resistance/higher capacitancestate (e.g., an insulative/higher impedance state) to a relatively lowerresistance/lower capacitance state (e.g., a conductive/lower impedancestate) or a Mott-like transition, indicating an abrupt change from aconductive/lower impedance state to an insulative/higher impedancestate, for example, may be inhibited from occurring in a CEM device. Forexample, for a CEM device operating in a low-impedance state, responsiveto current limiting by, for example, an external circuit element, suchas a resistive memory element, may operate to limit and/or constrain aconcentration of electrons that may be available to flow through the CEMdevice. In one embodiment, an additional resistor (or other type ofcurrent-limiting element) may be disposed in series with a CEM devicecoupled to a resistive memory element to limit a quantity of electronscapable of flowing through the CEM device. In another embodiment,current limiting within a CEM device may be achieved by selecting adopant type and atomic concentration, which may limit a number ofavailable carriers (e.g., holes or electrons) sufficient to bring abouta Mott or Mott-like transition. In an embodiment, reduction of an atomicconcentration of available holes may be achieved by utilizing an n-typedopant, which may render a material n-type and, accordingly, may inhibithole-induced Mott or Mott-like transitions. Accordingly, the Motttransition, previously defined herein as being in response to(n_(c))^(1/3)a≈0.26, (wherein n_(c) denotes a concentration ofelectrons, and wherein “a” denotes the Bohr radius) may, for example,prohibited from occurring. As described in detail herein, suchinhibiting, or at least restricting, of a Mott transition may permit aCEM device to operate in an absence of either a Mott transition or aMott-like transition. As described in reference to FIG. 1A, “a region ofan impedance profile that is absent Mott or Mott-like transition”corresponds to the region of the current density versus voltage profilethat includes points J_(OFF), J_(SET), and J_(COMP) (of FIG. 1A). Itshould be noted that additional approaches toward inhibiting Mott orMott-like transitions may be utilized, and claimed subject matter is notlimited in this respect.

FIG. 1A is a graphical representation of an impedance profile of adevice formed from a CEM according to an embodiment 100. Based, at leastin part, on a voltage applied to terminals of a CEM device, for example,the CEM device may be placed into a relatively low-impedance state or arelatively high-impedance state. For example, application of a voltageV_(SET) and a current density J_(SET) may bring about a transition ofthe CEM device to a relatively low-impedance memory state. In thiscontext, V_(SET) corresponds to a “turn-on” voltage, which means avoltage level at which a CEM device transitions from a high-impedancestate to a low-impedance state. Conversely, application of a voltageV_(RESET) and a current density J_(RESET) may bring about a transitionof the CEM device to a relatively high-impedance memory state. As shownin FIG. 1A, reference designator 110 illustrates the voltage range thatmay separate V_(RESET) from V_(SET).

In accordance with FIG. 1A, if a voltage signal at a sufficient level isapplied (e.g., exceeding a band-splitting potential) and theaforementioned Mott condition is satisfied (e.g., injected electronholes are of a population comparable to a population of electrons in aswitching region, for example), a CEM device may transition from arelatively low-impedance state to a relatively high-impedance state.This may correspond to point 108 of the voltage versus current densityprofile of FIG. 1A. At, or suitably near this point, electrons are nolonger screened and become localized near metal ions of the CEM formedwithin the CEM device. This correlation may result in a strongelectron-to-electron interaction potential, which may operate to splitthe bands to form a relatively high-impedance material. If the CEMdevice comprises a relatively high-impedance state, current may begenerated by transportation of electron holes. In certain embodiments,injection of a threshold current of electrons, at a threshold potentialapplied across terminals of a CEM device, may perform a “set” operation,which places the CEM device into a low-impedance state. In alow-impedance state, an increase in electrons may screen incomingelectrons and remove a localization of electrons, which may operate tocollapse the band-splitting potential, thereby giving rise to thelow-impedance state.

According to an embodiment, current in a CEM device may be controlled byan externally applied “compliance” condition, which may be determined atleast partially on the basis of an applied external current, which maybe limited during an operation to place the CEM device into a relativelyhigh-impedance state. This externally applied compliance current may, insome embodiments, also set a condition of a current density for asubsequent reset operation to place the CEM device into a relativelyhigh-impedance state. As shown in the particular implementation of FIG.1A, a current density J_(COMP), which may be applied during an operationat point 116 to place the CEM device into a relatively high-impedancestate, may determine a compliance condition for placing the CEM deviceinto a low-impedance state in a subsequent operation. As shown in FIG.1A, the CEM device may be subsequently placed into a low-impedance stateby application of a current density J_(RESET)≥J_(COMP) at a voltageV_(RESET) at point 108, at which J_(COMP) is externally applied.

In particular embodiments, points 108 and point 116 indicate Mott andMott-like transitions, respectively, in a CEM device. For example, inaccordance with FIG. 1A point 108 represents a feature on the voltageversus current density profile of FIG. 1A at which current densityabruptly transitions from a relatively unchanging relationship betweenthe applied voltage and current density (e.g., relatively flat) to asteep drop in current at the applied voltage V_(RESET). In anotherexample, point 116 represents a feature on the voltage versus currentdensity profile of FIG. 1A at which an increasing applied voltage maygive rise to a relatively large current flow. At point 116, voltage maybe reduced to accord with an abrupt transition of the CEM device from ahigh-impedance state to a low-impedance state, such as at region 104.

As pointed out above, a reset condition may occur in response to a Motttransition at point 108. As pointed out above, such a Mott transitionmay bring about a condition in a CEM device in which a concentration ofelectrons n approximately equals, or becomes at least comparable to, aconcentration of electron holes p. This condition may be modeledsubstantially in accordance with expression (1) as follows:

$\begin{matrix}{{{\lambda_{TF}n^{\frac{1}{3}}} = {\left. C \right.\sim 0.26}}{n = \left( \frac{C}{\lambda_{TF}} \right)^{3}}} & (1)\end{matrix}$In expression (1), λ_(TF) corresponds to a Thomas Fermi screeninglength, and C is a constant.

According to an embodiment, a current or current density in region 104of the voltage versus current density profile shown in FIG. 1A, mayexist in response to injection of holes from a voltage signal appliedacross terminals of a CEM device. Here, injection of holes may meet aMott transition criterion for the low-impedance state to high-impedancestate transition at current I_(MI) as a threshold voltage V_(MI) isapplied across terminals of a CEM device. This may be modeledsubstantially in accordance with expression (2) as follows:

$\begin{matrix}{{{I_{MI}\left( V_{MI} \right)} = {\frac{{dQ}\left( V_{MI} \right)}{dt} \approx \frac{Q\left( V_{MI} \right)}{t}}}{{Q\left( V_{MI} \right)} = {{qn}\left( V_{MI} \right)}}} & (2)\end{matrix}$Wherein Q(V_(MI)) corresponds to the charged injected (holes orelectrons) and is a function of an applied voltage. Injection ofelectrons and/or holes to enable a Mott transition may occur betweenbands and in response to threshold voltage V_(MI), and threshold currentI_(MI). By equating electron concentration n with a charge concentrationto bring about a Mott transition by holes injected by I_(MI) inexpression (2) according to expression (1), a dependency of such athreshold voltage V_(MI) on Thomas Fermi screening length λ_(TF) may bemodeled substantially in accordance with expression (3), as follows:

$\begin{matrix}{\mspace{76mu}{{{I_{MI}\left( V_{MI} \right)} = {\frac{Q\left( V_{MI} \right)}{t} = {\frac{{qn}\left( V_{MI} \right)}{t} = {\frac{q}{t}\left( \frac{C}{\lambda_{TF}} \right)^{3}}}}}{{J_{reset}\left( V_{MI} \right)} = {{J_{MI}\left( V_{MI} \right)} = {\frac{I_{MI}\left( V_{MI} \right)}{A_{CEM}} = {\frac{q}{A_{CEM}t} = {\frac{q}{A_{CEM}t}\left( \frac{C}{\lambda_{TF}} \right)^{3}}}}}}}} & (3)\end{matrix}$In which A_(CEM) is a cross-sectional area of a CEM device; andJ_(RESET) (V_(MI)) may represent a current density through the CEMdevice to be applied to the CEM device at a threshold voltage V_(MI),which may place the CEM device into a relatively high-impedance state.

According to an embodiment, the CEM device characterized in FIG. 1A, andin other figures herein, may comprise any transition metal oxide (TMO),such as, for example, perovskites, Mott insulators, charge exchangeinsulators, and Anderson disorder insulators. In particularimplementations, a CEM device may be formed from switching materials,such as nickel oxide, cobalt oxide, iron oxide, yttrium oxide, titaniumyttrium oxide, and perovskites, such as chromium doped strontiumtitanate, lanthanum titanate, and the manganate family includingpraseodymium calcium manganate, and praseodymium lanthanum manganite,just to provide a few examples. In particular, oxides incorporatingelements with incomplete “d” and “f” orbital shells, such as thoselisted above, may comprise sufficient impedance switching properties foruse in a CEM device. Other implementations may employ other transitionmetal compounds without deviating from claimed subject matter.

In one aspect, the CEM devices characterized in FIG. 1A, and in otherfigures herein, may comprise other types of transition metal oxidevariable impedance materials, though it should be understood that theseare exemplary only and are not intended to limit claimed subject matter.Nickel oxide (NiO) is disclosed as one particular TMO. NiO materialsdiscussed herein may be doped with extrinsic ligands, such as carbonyl(CO), which may establish and/or stabilize variable impedance propertiesand/or bring about a P-type operation in which a CEM device may be moreconductive in a low-impedance state (e.g., region 104 of FIG. 1A). Thus,in another particular example, NiO doped with extrinsic ligands may beexpressed as NiO:L_(x), where L_(x) may indicate a ligand element orcompound and x may indicate a number of units of the ligand for one unitof NiO. A value of x may be determined for any specific ligand and anyspecific combination of ligand with NiO or with any other transitionmetal compound simply by balancing valences. Other dopant ligands, whichmay bring about or enhance conductivity in a low-impedance state inaddition to carbonyl may include: nitrosyl (NO), triphenylphosphine(PPH₃), phenanthroline (C₁₂H₈N₂), bipyridine (C₁₀H₈N₂), ethylenediamine(C₂H₄(NH₂)₂), ammonia (NH₃), acetonitrile (CH₃CN), Fluoride (F),Chloride (Cl), Bromide (Br), cyanide (CN), sulfur (S), and others.

In this context, a “P-type” doped CEM device as referred to herein meansa first type of CEM comprising a particular molecular dopant thatcomprises increased electrical conductivity, relative to an undoped CEM,if the CEM device is operated in a low-impedance state, such as thelow-impedance state indicated by region 104 of FIG. 1A. Introduction ofa substitutional ligand, such as CO and NH₃, may operate to enhance theP-type nature of a NiO CEM. Accordingly, an attribute of P-typeoperation of a CEM device may include, at least in particularembodiments, an ability to tailor or customize electrical conductivityof a CEM, operated in a low-impedance state, by controlling an atomicconcentration of a P-type dopant in a CEM. In particular embodiments, anincreased atomic concentration of a P-type dopant may bring aboutincreased electrical conductivity of a CEM, although claimed subjectmatter is not limited in this respect.

In another embodiment, the CEM device characterized by FIG. 1A maycomprise other transition metal oxide variable impedance materials,having an atomic concentration of at least 85.0%, for example, with theremaining portion of the CEM comprising a dopant such as, for example,carbon or nitrogen (or nitrogen-containing or carbon-containingligands), though it should be understood that these are exemplary onlyand are not intended to limit claimed subject matter. Nickel oxide (NiO)is disclosed as one particular TMO. NiO materials discussed herein maybe doped with extrinsic nitrogen-containing ligands, which may stabilizevariable impedance properties. In particular, NiO variable impedancematerials disclosed herein may include nitrogen-containing molecules ofthe form C_(x)H_(y)N_(z) (wherein x≥0, y≥0, z≥0, and wherein at least x,y, or z comprise values >0) such as: ammonia (NH₃), cyano (CN⁻), azideion (N₃ ⁻) ethylene diamine (C₂H₈N₂), phen(1,10-phenanthroline)(C₁₂H₈N₂), 2,2′bipyridine (C₁₀,H₈N₂), ethylenediamine ((C₂H₄(NH₂)₂),pyridine (C₅H₅N), acetonitrile (CH₃CN), and cyanosulfanides such asthiocyanate (NCS⁻), for example. NiO variable impedance materialsdisclosed herein may include members of an oxynitride family(N_(x)O_(y), wherein x and y comprise whole numbers, and wherein x≥0 andy≥0 and at least x or y comprise values >0), which may include, forexample, nitric oxide (NO), nitrous oxide (N₂O), nitrogen dioxide (NO₂),or precursors with an NO₃ ⁻ ligand. In embodiments, metal precursorscomprising nitrogen-containing ligands, such as ligands amines, amides,alkylamides nitrogen-containing ligands with NiO by balancing valences.

In embodiments, depending on a molecular concentration of NiO:CO orNiO:NH₃, for example, which may vary from values approximately in therange of an atomic concentration of 0.1% to 10.0%, V_(RESET) andV_(SET), as shown in FIG. 1A, may vary approximately in the range of 0.1V to 10.0 V subject to the condition that V_(SET)≥V_(RESET). Forexample, in one possible embodiment, V_(RESET) may occur at a voltagefrom about 0.1 V to about 1.0 V, and V_(RESET) may occur at a voltage ofabout 1.0 V to about 2.0 V, for example. It should be noted, however,that variations in V_(SET) and V_(RESET) may occur based, at least inpart, on a variety of factors, such as atomic concentration of materialssuch as NiO:CO or NiO:NH₃ and other materials present in the CEM device,as well as other process variations, and claimed subject matter is notlimited in this respect.

Also in this context, an “electrode” as used herein means a conductivestructure comprising a surface that enables materials, such as materialsoperating to provide an electrical function, to be deposited or placedon or over the electrode. For example, in a CEM-based device, a metallicelectrode may comprise a significant atomic concentration of metal, mayoperate to conduct an electrical current to the CEM-based device incontact with the conductive metallic electrode. In embodiments, ametallic electrode may be constructed via a deposition process and maycomprise a titanium or titanium-based material, such as titanium nitride(TiN). In embodiments, a metallic electrode may comprise one or mored-block or f-block elements other than titanium, such as platinum,copper, aluminum, cobalt, nickel, tungsten, tungsten nitride, cobaltsilicide, ruthenium, ruthenium oxide, chromium, gold, palladium, indiumtin oxide, tantalum, silver, iridium or iridium oxide, or anycombination thereof, and claimed subject matter is not limited to anyparticular composition of conductive substrate material. It should benoted, however, that claimed subject matter is intended to embracemetallic electrodes of the form ML:L_(dopant), in which “M” indicates ametal ion, such as a d-block or f-block element, “L” indicates adominant ligand, such as oxygen in an NiO molecule, and in whichL_(dopant) comprises a dopant ligand, such as carbonyl (CO) in an NiO:COcomplex and NH₃ in NiO:NH₃ complex, just to name two possible examples.

Also in this context, a “layer” as the term is used herein, means amaterial composition which, in aggregation with one or more additionallayers on and/or beneath a particular layer, form a larger structure,such as a structure comprising one or more CEM devices. Thus, forexample, a wafer comprising one or more CEM devices may be formed byaccumulating or aggregating two or more layers deposited utilizing asuitable deposition process. In embodiments, structures comprising oneor more CEM devices may comprise any number of layers, such as twolayers, five layers, 10 layers, 50 layers, or a number of layers thatmay number into the thousands and beyond. In certain embodiments, alayered structure, such as a wafer, for example, may comprise substratelayers, CEM layers, layers comprising one or more conductive traces totraverse an area of the layered structure, layers comprising insulativematerial, as well as layers forming transistors, diodes, switches,passive circuit elements (e.g., capacitors, inductors, and so forth),interconnections between or among circuits, and a wide variety of layersto perform additional electrical functions, and claimed subject matteris not limited in this respect.

Further, in this context, a substrate may correspond to a first layer,or a first group of layers, of a wafer. Thus, for example, a transistor,logic device, diode, sensor, for example, may operate on or over asubstrate or first layer of a wafer. At a second layer of a wafer, or ata second group of layers of a wafer, one or more conductive traces toroute signals may disposed, as well as one or more interconnects, suchas optical interconnects, for example, may be positioned. Particulardevices, such as CEM devices, operating on or over first layer of awafer (or first group of layers of a wafer) may be physically separatedand/or electrically isolated by a second layer of a wafer (or secondgroup of layers of a wafer) by an insulating material, such as siliconnitride. Accordingly, in this context, a “wafer,” as the term is usedherein, means a multi-layered collection of devices, such as CEMdevices, which may perform a number of logic, switching, access, RF,signal reception and/or signal transmission, or other electrical and/orlogic functions, utilizing a plurality of layers forming a structurecomprising a fabricated wafer.

In particular embodiments, a deposition process may utilize two or moreprecursors to deposit components of, for example, NiO:CO or NiO:NH₃, forexample, onto a conductive metallic electrode positioned over asubstrate. In an embodiment, a CEM film may be deposited, for example,utilizing separate precursor molecules, AX and BY, substantially inaccordance with expression (4a), below:AX _((gas)) +BY _((gas)) =AB _((solid)) +XY _((gas))  (4a)

Wherein “A” of expression (4a) corresponds to a transition metal,transition metal compound, transition metal oxide, or any combinationthereof. In embodiments, a transition metal oxide may comprise nickel,but may comprise other transition metals, transition metal compounds,and/or transition metal oxides, such as aluminum, cadmium, chromium,cobalt, copper, gold, iron, manganese, mercury, molybdenum, nickel,palladium, rhenium, ruthenium, silver, tantalum, tin, titanium,vanadium, yttrium, and zinc (which may be linked to an anion, such asoxygen or other types of ligands), or combinations thereof, althoughclaimed subject matter is not limited in scope in this respect. Inparticular embodiments, compounds that comprise more than one transitionmetal oxide may also be utilized, such as yttrium titanate (YTiO₃).

In embodiments, “X” of expression (4a) may comprise a ligand, such as anorganic ligand, comprising amidinate (AMD), dicyclopentadienyl (Cp)₂,diethylcyclopentadienyl (EtCp)₂,Bis(2,2,6,6-tetramethylheptane-3,5-dionato) ((thd)₂), acetylacetonate(acac), bis(methylcyclopentadienyl) ((CH₃C₅H₄)₂), dimethylglyoximate(dmg)₂, 2-amino-pent-2-en-4-onato (apo)₂, (dmamb)₂ wheredmamb=1-dimethylamino-2-methyl-2-butanolate, (dmamp)2 wheredmamp=1-dimethylamino-2-methyl-2-propanolate,Bis(pentamethylcyclopentadienyl) (C₅(CH₃)₅)₂ and carbonyl (CO)₄.Accordingly, in some embodiments, nickel-based precursor AX maycomprise, for example, nickel amidinate (Ni(AMD)), nickeldicyclopentadienyl (Ni(Cp)₂), nickel diethyl cyclopentadienyl(Ni(EtCp)₂), Bis(2,2,6,6-tetramethylheptane-3,5-dionato)Ni(II)(Ni(thd)₂), nickel acetylacetonate (Ni(acac)₂),bis(methylcyclopentadienyl)nickel (Ni(CH₃C₅H₄)₂, Nickeldimethylglyoximate (Ni(dmg)₂), Nickel 2-amino-pent-2-en-4-onato(Ni(apo)₂), Ni(dmamb)₂ wheredmamb=1-dimethylamino-2-methyl-2-butanolate, Ni(dmamp)₂ wheredmamp=1-dimethylamino-2-methyl-2-propanolate,Bis(pentamethylcyclopentadienyl) nickel (Ni(C₅(CH₃)₅)₂, and nickelcarbonyl (Ni(CO)₄), just to name a few examples. In expression (4a),precursor “BY” may comprise an oxidizer, such as oxygen (O₂), ozone(O₃), nitric oxide (NO), hydrogen peroxide (H₂O₂), just to name a fewexamples. In other embodiments as will be described further herein,plasma may be used with an oxidizer to form oxygen radicals.

However, in particular embodiments, a dopant in addition to precursorsAX and BY may be utilized to form films utilized in a CEM device. Anadditional dopant ligand may co-flow with precursor AX to permitformation of compounds, substantially in accordance with expression(4b), below. In embodiments, a dopant comprising, for example, asammonia (NH₃), methane (CH₄), carbon monoxide (CO), or other materialmay be utilized, as may other ligands comprising carbon or nitrogen orother dopants listed above. Thus, expression (4a) may be modified toinclude an additional dopant ligand substantially in accordance withexpression (4b), below:AX _((gas))+(NH₃ or other ligand comprising nitrogen)+BY _((gas))=AB:NH_(3(solid)) +XY _((gas))  (4b)

It should be noted that concentrations, such as atomic concentration, ofprecursors, such as AX, BY, and NH₃ (or other ligand comprisingnitrogen) of expressions (4a) and (4b) may be adjusted so as to bringabout a final atomic concentration of nitrogen or carbon dopant, forexample, such as in the form of ammonia (NH₃) or carbonyl (CO)comprising an atomic concentration of between approximately 0.1% and15.0%. However, claimed subject matter is not necessarily limited to theabove-identified precursors and/or atomic concentrations. Rather,claimed subject matter is intended to embrace all precursors utilizedused in CEM film deposition, chemical vapor deposition, plasma chemicalvapor deposition, sputter deposition, physical vapor deposition, hotwire chemical vapor deposition, laser enhanced chemical vapordeposition, laser enhanced atomic layer deposition, rapid thermalchemical vapor deposition, spin on deposition, gas cluster ion beamdeposition, or the like, utilized in fabrication of CEM devices. Inexpressions (4a) and (4b), “BY” may comprise an oxidizer, such as oxygen(O₂), ozone (O₃), nitric oxide (NO), hydrogen peroxide (H₂O₂), just toname a few examples. In other embodiments, plasma may be used with anoxidizer (BY) to form oxygen radicals. Likewise, plasma may be used withthe doping species comprising material to form an activated species tocontrol the doping concentration of a CEM.

In particular embodiments, such as embodiments utilizing depositiontechniques, a metallic electrode may be exposed to precursors, such asAX and BY, as well as dopants comprising other materials (such asammonia or other ligands comprising metal-nitrogen bonds, including, forexample, nickel-amides, nickel-imides, nickel-amidinates, orcombinations thereof) in a heated chamber, which may attain, forexample, a temperature approximately in the range of 20.0° C. to 1000.0°C., for example, or between temperatures approximately in the range of20.0° C. and 500.0° C. in certain embodiments. In one particularembodiment, in which a deposition technique utilizes NiO:NH₃, forexample, is performed, chamber temperature ranges approximately in therange of 20.0° C. and 400.0° C. may be utilized. Responsive to exposureto precursor gases (e.g., AX, BY, NH₃, or other ligand comprisingnitrogen), such gases may be purged from the heated chamber fordurations approximately in the range of 0.5 seconds to 180.0 seconds. Itshould be noted, however, that these are merely examples of potentiallysuitable ranges of chamber temperature and/or time and claimed subjectmatter is not limited in this respect.

In certain embodiments, a single two-precursor cycle (e.g., AX and BY,as described with reference to expression 4(a)) or a singlethree-precursor cycle (e.g., AX, NH₃, CH₄, or other ligand comprisingnitrogen, carbon or other dopant material, and BY, as described withreference to expression 4(b)) utilizing deposition technique may bringabout a CEM device film comprising a thickness approximately in therange of 0.6 Å to 5.0 Å per cycle). Accordingly, in an embodiment, toform a CEM device film comprising a thickness of approximately 500.0 Åutilizing a deposition process in which CEM films comprise a thicknessof approximately 0.6 Å, 800-900 cycles, for example, may be utilized. Inanother embodiment, utilizing a film deposition process in which filmscomprise approximately 5.0 Å, 100 two-precursor cycles, for example. Itshould be noted that deposition processes may be utilized to form CEMdevice films having other thicknesses, such as thicknesses approximatelyin the range of 1.5 nm and 150.0 nm, for example, and claimed subjectmatter is not limited in this respect.

In particular embodiments, responsive to one or more two-precursorcycles (e.g., AX and BY), or three-precursor cycles (AX, NH₃, CH₄, orother ligand comprising nitrogen, carbon or other dopant and BY), of adeposition technique, a CEM device film may undergo in situ annealing,which may permit improvement of film properties or may be used toincorporate a dopant, such as in the form of carbonyl or ammonia, in theCEM device film. In certain embodiments, a chamber may be heated to atemperature approximately in the range of 20.0° C. to 1000.0° C.However, in other embodiments, in situ annealing may be performedutilizing chamber temperatures approximately in the range of 100.0° C.to 800.0° C. In situ annealing times may vary from a durationapproximately in the range of 1.0 seconds to 5.0 hours. In particularembodiments, annealing times may vary within more narrow ranges, suchas, for example, from approximately 0.5 minutes to approximately 180.0minutes, for example, and claimed subject matter is not limited in theserespects.

In particular embodiments, a CEM device manufactured in accordance withthe above-described process may exhibit a “born on” property in whichthe device exhibits relatively low impedance (relatively highconductivity) immediately after fabrication of the device. Accordingly,if a CEM device is integrated into a larger electronics environment, forexample, at initial activation a relatively small voltage applied to aCEM device may permit a relatively high current flow through the CEMdevice, as shown by region 104 of FIG. 1A. For example, as previouslydescribed herein, in at least one possible embodiment, V_(RESET) mayoccur at a voltage equal to about 0.1 V to about 1.0 V, and V_(SET) mayoccur at a voltage equal to about 1.0 V to about 2.0 V, for example.Accordingly, electrical switching voltages operating in a range ofapproximately 2.0 V, or less, may permit operations of the CEM device.In embodiments, such relatively low voltage operation may reducecomplexity, cost, and may provide other advantages over competing memoryand/or switching device technologies.

FIG. 1B is an illustration of an embodiment 150 of a CEM device and aschematic diagram of an equivalent circuit of the CEM device. Aspreviously mentioned, a correlated electron device, such as a correlatedelectron switch, a CEM-based diode, or other type of device utilizingone or more correlated electron materials may comprise a variable orcomplex impedance device that may comprise characteristics of bothvariable resistance and variable capacitance. In other words, impedancecharacteristics for a CEM variable impedance device, such as a devicecomprising a metallic electrode 160, CEM 170, and conductive overlay180, may depend at least in part on resistance and capacitancecharacteristics of the device if measured across device terminals 122and 130. In an embodiment, an equivalent circuit for a variableimpedance device may comprise a variable resistor, such as variableresistor 126, in parallel with a variable capacitor, such as variablecapacitor 128. Of course, although a variable resistor 126 and variablecapacitor 128 are depicted in FIG. 1B as comprising discrete components,a variable impedance device, such as device of embodiment 150, maycomprise a substantially homogenous CEM and claimed subject matter isnot limited in this respect.

Table 1, below, depicts an example truth table for an example variableimpedance device, such as the device of embodiment 150.

TABLE 1 Correlated Electron Switch Truth Table Resistance CapacitanceImpedance R_(high)(V_(applied)) C_(high)(V_(applied))Z_(high)(V_(applied)) R_(low)(V_(applied)) C_(low)(V_(applied))~0Z_(low)(V_(applied))

In an embodiment, Table 1 shows that a resistance of a variableimpedance device, such as the device of embodiment 150, may transitionbetween a low-impedance state and a substantially dissimilar,high-impedance state as a function at least partially dependent on avoltage applied across a CEM device. In an embodiment, an impedanceexhibited at a low-impedance state may be approximately in the range of10.0 to 100,000.0 times lower than an impedance exhibited in ahigh-impedance state. In other embodiments, an impedance exhibited at alow-impedance state may be approximately in the range of 5.0 to 10.0times lower than an impedance exhibited in a high-impedance state, forexample. It should be noted, however, that claimed subject matter is notlimited to any particular impedance ratios between high-impedance statesand low-impedance states. Table 1 shows that a capacitance of a variableimpedance device, such as the device of embodiment 150, may transitionbetween a lower capacitance state, which, in an example embodiment, maycomprise approximately zero (or very little) capacitance, and a highercapacitance state that is a function, at least in part, of a voltageapplied across a correlated electron switch.

FIG. 2 is a graphical representation of an impedance profile of a deviceformed from a correlated electron material according to an embodiment200. In embodiment 200, the impedance profile relates the response of aCEM device to a voltage applied across first and second terminals of theCEM device. In particular embodiments, a CEM device comprises a “bornon” property in which the device may exhibit relatively low impedance(relatively high conductivity) immediately after fabrication of thedevice such as shown in region 204A of FIG. 2. In certain embodiments, aborn-on property of a CEM device may operate in a first quadrant (Q1),in which a current may flow in a first direction responsive to apositive voltage applied across a CEM device. A CEM device may operatein a manner that is symmetrical with respect to current through the CEMdevice in response to a voltage applied across the device, such asdescribed with respect to embodiment 200 of FIG. 2.

In this context, “symmetrical” operation of the CEM device may bedefined as a device that permits bidirectional current flow, whichrefers to current flow in a first direction responsive to application ofa voltage comprising a first sense (such as positive) and permitscurrent flow in a second direction, which is a polar opposite the firstdirection, responsive to application of voltage comprising a secondsense (such as negative). Additionally, current flow in the seconddirection may be of substantially the same magnitude as current flow inthe first direction under a voltage of substantially the same magnitude.Further, in the context of “symmetrical” operation of a CEM device, suchas a CEM diode, for example, “symmetrical” does not necessarily indicatemirror-like operation of a CEM device with respect to current throughdevice in response to a voltage applied across terminals of the device.Accordingly, variations (e.g., ±2.5%, ±5.0%, ±10.0%) in magnitudes ofV_(SET) values as well as V_(RESET) may be embraced by the definition ofsymmetrical operation of a CEM device. In addition, variations inmagnitudes of I_(RST) and I_(COMP) may be embraced by the definition ofsymmetrical operation of a CEM device. Further in this context, “partialsymmetry” of a CEM device means symmetrical operation over at least theportion of the impedance profile of the CEM device that spans −V_(SET)to +V_(SET).

In the embodiment of FIG. 2, as a voltage applied across terminals of aCEM device is increased from a value of, for example, 0.0 volts (V), acurrent flow may occur in response. As an applied voltage is increased,such as to V_(RST), current flow through a CEM device may increase to alevel I_(RST) before beginning a steep decline, such as at point 215A.In embodiments, current flow may decline to a smaller value, which mayapproach 20.0% of I_(RST), 10.0% of I_(RST), 1.0%, 0.1% of I_(RST), oran even smaller fraction of I_(RST), for example. As previouslymentioned herein, a steep decline, such as from a current of I_(RST) toa fraction of I_(RST), may be indicative of region of operation thatindicates a Mott transition. As a voltage applied across a CEM device isincreased beyond V_(RST), the device may begin operating in a relativelyhigh-impedance state, such as shown in region 205A of FIG. 2. It shouldbe noted that in particular embodiments, responsive to application of adecreasing voltage, such as a voltage less than V_(RST), a CEM devicemay operate in region 206A of FIG. 2.

Returning to operation of a CEM device in region 205A (a relativelyhigh-impedance state), applying an increasing voltage across first andsecond terminals of the CEM device may give rise to a relatively steepincrease in current flow, at V_(SET), until current flow through the CEMdevice reaches a compliance current, indicated as I_(COMP) in FIG. 2.Accordingly, at point 216A, which may represent a region of operationthat indicates a Mott-like transition. At point 216A, the CEM device maytransition (e.g., turn-on) to a low-impedance state, such as shown asregion 204A of FIG. 2. In embodiments, decreasing a voltage appliedacross first and second terminals of a CEM device, such as to voltagesapproaching values of 0.0 V, as well as voltages comprising negativevalues, may give rise to operation of the CEM device in region 204A ofFIG. 2. As a voltage applied across terminals of a CEM device is furtherdecreased (e.g., to comprise larger negative values), such as to voltage−V_(RST), may give rise to a current flow such as −I_(RST), for example.As an applied voltage is further decreased (e.g., to comprise largernegative values) to a level less than −V_(RST), current flow through CEMdevice may change from a level −I_(RST), such as at point 215B, to asmaller negative value, which may approach 20.0% of −I_(RST), 10.0% of−I_(RST), 1.0% of −I_(RST), 0.1% of −I_(RST), or to an even smallerfraction of −I_(RST), for example. As previously mentioned herein, anabrupt, steep transition, such as from a current of −I_(RST) to afraction of −I_(RST) may represent a Mott transition within a CEMdevice. As a voltage applied across terminals of a CEM device is furtherdecreased to values less than −V_(RST), the CEM device may operate in arelatively high-impedance state, such as in region 205B of FIG. 2. Itshould be noted that in particular embodiments, responsive toapplication of an increasing voltage (e.g., a voltage approaching 0.0),such as a voltage greater than −V_(RST), a CEM device may operate inregion 206B of FIG. 2.

Returning to operation of a CEM device in region 205B, applying andecreasing voltage (e.g., to comprise larger negative values) acrossfirst and second terminals of the CEM device may give rise to arelatively large negative current flow, such as at −V_(SET) untilcurrent flow through the CEM device reaches a compliance current,indicated as −I_(COMP) in FIG. 2. Accordingly, at point 216B a Mott-liketransition may occur, in which the CEM device may transition to alow-impedance state, such as shown in region 204B of FIG. 2. Inembodiments, increasing a voltage across terminals of a CEM device, suchas to voltage levels of 0.0 V, may give rise to operation of the CEMdevice in region 204B of FIG. 2.

FIG. 3 is a graphical representation of an impedance profile of a CEMdevice operating as a diode and comprising at least partially symmetricoperation with respect to impedance of the CEM device. Embodiment 300,for example, may be brought about by limiting electrical currentpermitted to flow through a CEM device. In embodiments, responsive tocurrent limiting by, for example, a circuit element, such as a resistivememory element, and/or an external resistive circuit element, mayoperate to limit and/or to constrain a quantity of electrons that may beavailable to flow through the CEM device. Accordingly, a Motttransition, such as may occur responsive to a concentration of electronsn approaching a concentration of electron holes p (substantially inaccordance with expression (1)) may be inhibited. Thus, a CEM device mayoperate in a region of an impedance profile that is absent a Mott orMott-like transition.

As shown in FIG. 3, a CEM device may comprise symmetrical operation withrespect to impedance of the device. Thus, responsive to application of apositive voltage across first and second terminals of the device, suchas V_(RST) or V_(SET), a positive current may flow. Additionally,responsive to application of a negative voltage across first and secondterminals of the device, such as −V_(SET) or −V_(RST), a negativecurrent may flow. Further, in particular embodiments, the impedanceprofile of a CEM device, may be adapted to operate in an absence of aMott or Mott-like transition. Thus, for example, a region of animpedance profile that indicates an absence of a Mott or Mott-liketransition indicated by points 216A, 216B, 215A, and 215B, of thecurrent versus voltage profile of FIG. 2. A CEM device may additionallycomprise a monotonically increasing impedance profile over a particularoperating voltage domain, which, in this context, means that forincreasing voltages applied across first and second terminals, anincreased voltage applied across the CEM device gives rise to anincreased current flowing through the CEM device. For example, referringto FIG. 3, as an applied voltage is increased from −V_(SET), to−V_(RST), to V_(RST), and to V_(SET) current flowing through the CEMdevice likewise increases.

FIG. 4 is a graphical representation of a voltage versus current profileof a resistive memory element according to an embodiment 400. Inparticular embodiments, a resistive memory element may operate in amanner that is distinct from operation of CEM devices. For example, aresistive memory element (which may be referred to as a RERAM memoryelement) may comprise, for example, a metallic oxide or oxide filamentin which, in a first operating state, a particular voltage signalapplied between first and second terminals of the resistive memoryelement may operate to permit charges to flow within the memory element.In a second operating state, an absence of a metallic oxide or oxidefilament of the RERAM memory element may inhibit movement of chargesbetween terminals of the memory element. In another embodiment, aresistive memory element, such as a phase change random access memory(PCRAM) element, may operate in a first material phase, such as anamorphous material phase, to give rise to relatively limited currentflow between terminals of the memory element in response to an appliedvoltage. In a second material phase of a PCRAM element, such as acrystalline material phase, a relatively larger current may flow betweenterminals of a resistive memory element.

In another embodiment of a resistive memory element, such as aconductive bridging random access memory (which may be referred to as aCBRAM) a first resistive state of a memory element may occur in responseto formation of metallic filaments. A second resistive state of a CBRAMmay occur in response to an absence of formation of the metallicfilaments. In another embodiment of a resistive memory element, such asa nanotube random access memory (which may be referred to as a NanotubeRAM or NRAM), movement of carbon nanotubes to form a conductive path maybring about a first resistive state, which may comprise a relativelyconductive state, of a memory element. A second resistive state of aNano-RAM or NRAM may be brought about by movement of carbon nanotubes,so as to restrict formation of a conductive path, may bring about asecond resistive state, such as a relatively insulative state, of thememory element. In another embodiment, a resistive memory element maycorrespond to spin-transfer torque magnetic random access memory(STT-MRAM) that utilizes a tunneling magnetoresistive effect for readingfrom a memory element and a spin-transfer torque (STT) effect forwriting to a memory element. It should be noted that claimed subjectmatter is intended to embrace all types of resistive memory elements,which may operate in a manner that is distinct from operation of CEMdevices, wherein a logic state may be encoded as a resistance level, ora range of resistance levels, which may be sensed across terminals ofthe memory element.

As shown in FIG. 4, a resistive memory element may comprise distinctresistances, such as R_(OFF) and R_(ON), for example, which maycorrespond to high-resistivity (R_(OFF)) and low-resistivity (R_(ON))states of a resistive random access memory (RERAM or RRAM). Inembodiments, a resistive memory element comprising a voltage versuscurrent profile in accordance with that of FIG. 4 may correspond to avariety of resistive memory elements.

In the embodiment of FIG. 4, at quadrant 1 (Q1), for a resistive memoryelement in a high-resistance state (e.g., R_(OFF)), a comparativelysmall current may flow responsive to application of a small positivevoltage such as V_(FWD), applied across first and second terminals ofthe memory element. As a voltage applied across terminals of theresistive memory element increases, such as to V_(RD), which correspondsto a read voltage at which the high/low resistance state of theresistive memory element may be determined, a larger electrical currentmay be permitted to flow through the device. As a voltage applied acrossthe resistive memory element continues to increase, such as to V_(SET),the memory element may transition from a high-resistance state to alow-resistance state (e.g., R_(OFF)). Accordingly, responsive to atransition to a low-resistance state, an increased current may bepermitted to flow through the resistive memory element. As an appliedvoltage is decreased, a decreasing current may flow through theresistive memory element. In embodiments, decreasing a voltage appliedacross terminals of a resistive memory element, such as to voltagescomprising values of 0.0 V as well as to negative voltages, such as−V_(FWD) at quadrant 3 (Q3), a current may flow in an oppositedirection. As a voltage applied across terminals of the device isdecreased (e.g., to comprise larger negative values), such as to −V_(RD)and to −V_(SET), a resistive memory element may transition from alow-resistance (R_(ON)) state to a high-resistance state (R_(OFF)). As avoltage applied across terminals of the resistive memory element,current flowing through the memory element may correspondingly decrease.

Thus, the resistive memory element of FIG. 4 comprises bipolaroperation. In this context, “bipolar” operation of a resistive memoryelement means application of voltages of a first polarity and a secondpolarity, such as a positive polarity and a negative polarity, forexample, to bring about differing resistive states of a material. Forexample, in the embodiment of FIG. 4, to bring about a transition of aresistive memory element from a high-resistance state (R_(OFF)) to alow-resistance state (R_(ON)), a positive voltage, such as V_(SET) maybe applied. Further, to transition the resistive memory element from alow-resistance state to a high-resistance state (e.g., R_(ON) toR_(OFF)) a negative voltage, such as −V_(SET) may be applied.

FIG. 5 is a graphical representation of an impedance profile of acompound device comprising a CEM device operating as a diode in serieswith a resistive memory element according to an embodiment 500. Elementsof the voltage versus current profile of the CEM device operating as adiode of FIG. 3 and elements of the voltage versus current profile ofthe resistive memory element of FIG. 4 are represented on the impedanceprofile of FIG. 5. It should be noted, however, that the voltage V_(SET)depicted in FIG. 3, has been renamed to V_(SETC) in FIG. 5 so as tocorrespond to the voltage at which a “set” operation occurs within a CEMdevice. It should additionally be noted that the voltage V_(SET) of FIG.4 has been renamed to V_(SETR) in FIG. 5 so as to correspond to thevoltage at which a “set” operation occurs within a resistive memoryelement. Further, in FIG. 5, V_(RD) corresponds to a read voltage atwhich the high/low resistance state of the resistive memory element maybe determined. Thus, in an embodiment, ±V_(SETC), ±V_(RD), and ±V_(SETR)may comprise the following voltage ranges:V _(SETC)≈1.3 to 1.8 V,−V _(SETC)≈−1.3 to −1.8 VV _(RD)≈+1.5 V,−V _(RD)=−1.5 VV _(SETR)≈2.5 to 3.0 V,−V _(SETR)≈−2.5 to −3.0 VThus, as shown in FIG. 5, a compound device that includes a CEM deviceoperating as a diode in series with a resistive memory element maycomprise a high-impedance state for applied voltages between −V_(SETC)and V_(SETC) (e.g., −1.2 V to 1.2 V). In particular embodiments, suchhigh-impedance operation may be advantageous when a resistive memoryelement operates in a low-impedance state (e.g., R_(ON)). Under suchconditions, R_(ON) current, which may be characterized as leakagecurrent flowing when relatively small voltages are applied across theterminals of the resistive memory cell, may be limited by thehigh-impedance operation of the CEM device in series with the resistivememory element. In FIG. 5, arrows 515A and 515B indicate a reduction inleakage current between −V_(SETC) and V_(SETC). At voltages between+V_(RD) and +V_(SETR), as well as between −V_(SETR) and −V_(RD), whichcorresponds to voltages at which an increased current may flow throughthe CEM device, the resistance behavior of the compound predominantlyresponsive to internal resistances of the resistive memory cell.

FIG. 6A is a graphical representation of an operating envelope, withrespect to impedance, of a compound device, such as the compound deviceof FIG. 6B, according to an embodiment 600. In the embodiment of FIG.6B, a compound device comprises CEM device 610 coupled in series withresistive memory element 620, which may be characterized by theimpedance profile of FIG. 6A, for example. As shown in FIG. 6A and asdescribed previously with reference to FIG. 5, a compound device maycomprise significantly reduced leakage current at applied voltagesbetween −1.2V and 1.2V. In particular embodiments, voltages of about−1.2 V and 1.2 V correspond to turn-on voltages for CEM device 610,which, in this context, refers to a voltage at which strong conductionof an electrical current may occur. However, as previously mentioned, inview of resistance introduced by a resistive memory element in serieswith CEM device 610, an electrical current may remain below a thresholdat which a Mott transition may occur (e.g. transition fromhigh-impedance to low-impedance). In other embodiments, CEM device 610may be designed, such as via selective doping, for example, so as tothat inhibit a Mott transition.

Thus, in the embodiment of FIG. 6A, at quadrant 1 (Q1), for a compounddevice operating in a high-resistance state (e.g., R_(OFF)), arelatively small current may flow responsive to application of a smallpositive voltage such as voltages less than, for example, 1.2 V. As avoltage applied across the compound device increases, such as to 1.5 V,which may correspond to a voltage at which the high/low resistance stateof the resistive memory element of the compound device may be determined(read voltage), a larger electrical current may be permitted to flow. Asa voltage applied across the compound device continues to increase, suchas to 3.0 V, for example, the memory element may transition from ahigh-resistance state (e.g., R_(OFF)) to a low-resistance state (e.g.,R_(ON)). Accordingly, a relatively large current may be permitted toflow through the resistive memory element. As an applied voltage isdecreased, a correspondingly decreased current may flow through thecompound device. In embodiments, decreasing a voltage applied acrossterminals of a resistive memory element, such as to voltages of 0.0 V aswell as to negative voltages, such as −1.2 V at quadrant 3 (Q3), acurrent may flow in an opposite direction. As a voltage across acompound device is further decreased, such as to −2.5 V to −3.0 V, acompound device may transition from a low-impedance (R_(ON)) state to ahigh-impedance state (R_(OFF)). As a voltage applied to terminals of aresistive memory element is increased, so as to return to 0.0 V, currentflowing through the compound device may decrease correspondingly.

FIG. 7A is a schematic diagram showing an arrangement of compounddevices, such as those illustrated in FIG. 6B, according to anembodiment 700. It should be noted that a wide variety of additionalarrangements of compound devices are possible, and claimed subjectmatter is not limited to any particular arrangement of compound devices.In FIG. 7A, compound devices are arranged in a cross point array, inwhich common top electrode CT₁ is common among CEM device t₁b₁ and CEMdevice t₁b₂, and common top electrode CT₂ is common among CEM devicet₂b₁ and CEM device t₂b₂. Resistive memory elements 620A, 620B, 620C,and 620D are arranged in series with CEM devices t₁b₁, t₁b₂, t₂b₁, andt₂b₂ (respectively). In FIG. 7A, and bottom electrode CB₁ is commonamong CEM device t₁b₁ and CEM device t₂b₁, and, and bottom electrode CB₂is common among CEM device t₁b₂ and CEM device t₂b₂. Thus, common topelectrodes CT₁ and CT₂ may operate in combination with common bottomelectrodes CB₁ and CB2 to read from and to write to memory elements ofCEM devices t₁b₁, t₁b₂, t₂b₁, and t₂b₂. The cross point memoryarrangement of FIG. 7A may permit a circuit, for example, to select anindividual CEM device while deselecting the remaining CEM devices.However, common top electrodes CT₁ and CT₂ and common bottom electrodesb₁ and b₂ may perform different functions, and claimed subject matter isnot limited in this respect.

Thus, in one example, a 3.0 V signal applied to common top electrode CT₁and a 0.0 V signal applied to common bottom electrode CB₁ may bringabout a voltage across CEM device t₁b₁ sufficient to place the CEMdevice into a low-impedance state. Accordingly, resistive memory element620A may undergo a “set” operation to place the resistive memory elementinto a R_(on) state. However, CEM device t₁b₂, CEM device t₂b₁, and CEMdevice t₂b₂ may remain deselected, thus preserving the R_(on)/R_(off)states of memory elements 620B, 620C, and 620D.

FIG. 7B is a schematic diagram showing an arrangement of stackedcompound devices, such as the compound devices illustrated in FIG. 7A,according to an embodiment 750. In the embodiment of FIG. 7B, resistivememory elements 620A, 620B, 620C, and 620D are arranged in a cross pointarray between two metal layers, such as a bottom metal layer and metallayer 1. In a manner similar to that described with respect to FIG. 7A,common top electrodes CT_(L1,T1) and CT_(L1,T2) of metal layer 1 mayoperate in combination with common bottom electrodes CB_(L1,T1) andCB_(L1,T2) of the bottom metal layer to read from and to write to one ofmemory elements 620A, 620B, 620C, and 620D while deselecting theremaining memory elements. Likewise, common top electrodes CT_(L2,T1)and CT_(L2,T2) of metal layer 2 may operate in combination with commontop electrodes CT_(L1,T1) and CT_(L1,T2) of metal layer 1 to read fromand to write to memory one of memory elements 621A, 621B, 621C, and 621Dwhile deselecting the remaining memory elements.

It should be noted that the arrangement of stacked compound devices ofFIG. 7B may be extended to include numerous additional metal layers,such as metal layer 3, metal layer 4, and so forth, up to as many metallayers as wafer fabrication process technologies can support. In oneembodiment, for example, the cross point memory arrangement of FIG. 7Bmay be extended in the “Z” dimension to include a bottom metal layer and64 metal layers disposed over the bottom metal layer. In addition, thearrangement of stacked compound devices of FIG. 7B may be extended inthe “X” and the “Y” dimensions to include additional resistive memoryelements and CEM devices in an X-Y plane. In one embodiment, forexample, a cross point memory array arrangement that accords with thatof FIG. 7B a comprise 64 metal layers and having several million,billions, or any larger number of resistive memory elements coupled inseries with CEM devices. It should be noted that claimed subject matteris intended to embrace virtually any two-dimensional orthree-dimensional layout of resistive memory elements.

FIG. 8 is an illustration of a resistive memory element implemented onor over a CEM device at a back-end-of-line of a wafer fabricationprocess according to an embodiment 800. Although FIG. 8 illustrates onlya single arrangement of a CEM device and resistive memory element,claimed subject matter is intended to embrace a wide variety ofarrangements of CEM devices and resistive memory elements. Additionally,although the embodiment of FIG. 8 shows a resistive memory elementdisposed on a CEM device, claimed subject matter is not limited in thisrespect. In other embodiments, a CEM device may be disposed on or over aresistive memory element, for example.

In the embodiment of FIG. 8, a CEM device may be fabricated or formed toconnect directly with metal layers, such as metal layer t₁, which mayoperate as a wordline as described in reference to FIG. 7A, and metallayer b₁, which may operate as a bitline, also as described withreference to FIG. 7A. Conductive via 820 may contact metal layer t₁, andmay provide electrical connection between conductive via 820 andelectrode 830 of resistive memory material 840. Resistive memorymaterial 840 may contact CEM device 850, which may operate as a diode,as previously described herein. CEM device 850 may contact conductivevia 860, which may provide electrical connection between CEM device 850metal layer b₁.

FIG. 9 is a flowchart for a method of operating a memory device using aCEM device according to an embodiment 900. Example implementations, suchas described in FIG. 9, and any other figures described herein, mayinclude blocks in addition to those shown and described, fewer blocks orblocks occurring in an order different than may be identified, or anycombination thereof. The method may begin at block 910, which maycomprise applying a voltage signal to a CEM device coupled in serieswith a resistive memory element. In particular embodiments, a resistivememory element may comprise memory elements that utilize an oxide layerin which an applied voltage signal operates to inhibit movement ofcharges across a memory element or operates to permit movement ofcharges across the memory element. In another embodiment, a resistivememory element may correspond to spin-transfer torque magnetic randomaccess memory (STT-MRAM) that utilize tunneling magnetoresistance effectfor reading from a memory element and a spin-transfer torque (STT)effect for writing to a memory element. In another embodiment, aresistive memory element may correspond to a nano-RAM memory element inwhich a memory state may is based, at least in part, on a position ofcarbon nano tubes.

The method of FIG. 9 may continue at block 920, which may compriselimiting electrical current flow through the CEM device to maintainoperation of the CEM device along a region of an impedance profile thatis absent a Mott or Mott-like transition. For example, for a CEM deviceoperating in a low-impedance state, responsive to current limiting by,for example, an external circuit element, such as a resistive memoryelement, may operate to limit and/or constrain a concentration ofelectrons that may be available to flow through the CEM device.

FIG. 10 is a flowchart for a method of operating a memory device using aCEM device according to an embodiment 1000. Example implementations,such as described in FIG. 10, and any other figures described herein,may include blocks in addition to those shown and described, fewerblocks or blocks occurring in an order different than may be identified,or any combination thereof. The method may begin at block 1010, whichmay comprise forming one or more resistive memory elements having firstterminals and second terminals. In particular embodiments, a resistivememory element may comprise memory elements that utilize an oxide layerin which an applied voltage signal operates to inhibit movement ofcharges across a memory element or operates to permit movement ofcharges across the memory element. In another embodiment, a resistivememory element may correspond to spin-transfer torque magnetic randomaccess memory (STT-MRAM) that utilize tunneling magnetoresistance effectfor reading from a memory element and a spin-transfer torque (STT)effect for writing to a memory element. In another embodiment, aresistive memory element may correspond to a nano-RAM memory element inwhich a memory state may is based, at least in part, on a position ofcarbon nano tubes.

The method of FIG. 10 may continue at block 1020, which may compriseforming a CEM device to be coupled in series with at least one of theone or more resistive memory elements, the CEM device to operate toperform read operations or write operations in a region of an impedanceprofile that is absent a Mott or Mott-like transition during the readoperations or the write operations of the at least one of the one ormore resistive memory elements.

In the preceding description, in a particular context of usage, such asa situation in which tangible components (and/or similarly, tangiblematerials) are being discussed, a distinction exists between being “on”and being “over.” As an example, deposition of a substance “on” asubstrate refers to a deposition involving direct physical and tangiblecontact in the absence of an intermediary, such as an intermediarysubstance (e.g., an intermediary substance formed during an interveningprocess operation), between the substance deposited and the substrate inthis latter example; nonetheless, deposition “over” a substrate, whileunderstood to potentially include deposition “on” a substrate (sincebeing “on” may also accurately be described as being “over”), isunderstood to include a situation in which one or more intermediaries,such as one or more intermediary substances, are present between thesubstance deposited and the substrate so that the substance deposited isnot necessarily in direct physical and tangible contact with thesubstrate.

A similar distinction is made in an appropriate particular context ofusage, such as in which tangible materials and/or tangible componentsare discussed, between being “beneath” and being “under.” While“beneath,” in such a particular context of usage, is intended tonecessarily imply physical and tangible contact (similar to “on,” asjust described), “under” potentially includes a situation in which thereis direct physical and tangible contact, but does not necessarily implydirect physical and tangible contact, such as if one or moreintermediaries, such as one or more intermediary substances, arepresent. Thus, “on” is understood to mean “immediately over” and“beneath” is understood to mean “immediately under.”

It is likewise appreciated that terms such as “over” and “under” areunderstood in a similar manner as the terms “up,” “down,” “top,”“bottom,” and so on, previously mentioned. These terms may be used tofacilitate discussion, but are not intended to necessarily restrictscope of claimed subject matter. For example, the term “over,” as anexample, is not meant to suggest that claim scope is limited to onlysituations in which an embodiment is right side up, such as incomparison with the embodiment being upside down, for example. Anexample includes a flip chip, as one illustration, in which, forexample, orientation at various times (e.g., during fabrication) may notnecessarily correspond to orientation of a final product. Thus, if anobject, as an example, is within applicable claim scope in a particularorientation, such as upside down, as one example, likewise, it isintended that the latter also be interpreted to be included withinapplicable claim scope in another orientation, such as right side up,again, as an example, and vice-versa, even if applicable literal claimlanguage has the potential to be interpreted otherwise. Of course,again, as always has been the case in the specification of a patentapplication, particular context of description and/or usage provideshelpful guidance regarding reasonable inferences to be drawn.

Unless otherwise indicated, in the context of the present disclosure,the term “or” if used to associate a list, such as A, B, or C, isintended to mean A, B, and C, here used in the inclusive sense, as wellas A, B, or C, here used in the exclusive sense. With thisunderstanding, “and” is used in the inclusive sense and intended to meanA, B, and C; whereas “and/or” can be used in an abundance of caution tomake clear that all of the foregoing meanings are intended, althoughsuch usage is not required. In addition, the term “one or more” and/orsimilar terms is used to describe any feature, structure,characteristic, and/or the like in the singular, “and/or” is also usedto describe a plurality and/or some other combination of features,structures, characteristics, and/or the like. Furthermore, the terms“first,” “second,” “third,” and the like are used to distinguishdifferent aspects, such as different components, as one example, ratherthan supplying a numerical limit or suggesting a particular order,unless expressly indicated otherwise. Likewise, the term “based on”and/or similar terms are understood as not necessarily intending toconvey an exhaustive list of factors, but to allow for existence ofadditional factors not necessarily expressly described.

Furthermore, it is intended, for a situation that relates toimplementation of claimed subject matter and is subject to testing,measurement, and/or specification regarding degree, to be understood inthe following manner. As an example, in a given situation, assume avalue of a physical property is to be measured. If alternativelyreasonable approaches to testing, measurement, and/or specificationregarding degree, at least with respect to the property, continuing withthe example, is reasonably likely to occur to one of ordinary skill, atleast for implementation purposes, claimed subject matter is intended tocover those alternatively reasonable approaches unless otherwiseexpressly indicated. As an example, if a plot of measurements over aregion is produced and implementation of claimed subject matter refersto employing a measurement of slope over the region, but a variety ofreasonable and alternative techniques to estimate the slope over thatregion exist, claimed subject matter is intended to cover thosereasonable alternative techniques, even if those reasonable alternativetechniques do not provide identical values, identical measurements oridentical results, unless otherwise expressly indicated.

It is further noted that the terms “type” and/or “like,” if used, suchas with a feature, structure, characteristic, and/or the like, using“optical” or “electrical” as simple examples, means at least partiallyof and/or relating to the feature, structure, characteristic, and/or thelike in such a way that presence of minor variations, even variationsthat might otherwise not be considered fully consistent with thefeature, structure, characteristic, and/or the like, do not in generalprevent the feature, structure, characteristic, and/or the like frombeing of a “type” and/or being “like,” (such as being an “optical-type”or being “optical-like,” for example) if the minor variations aresufficiently minor so that the feature, structure, characteristic,and/or the like would still be considered to be predominantly presentwith such variations also present. Thus, continuing with this example,the terms optical-type and/or optical-like properties are necessarilyintended to include optical properties. Likewise, the termselectrical-type and/or electrical-like properties, as another example,are necessarily intended to include electrical properties. It should benoted that the specification of the present disclosure merely providesone or more illustrative examples and claimed subject matter is intendedto not be limited to one or more illustrative examples; however, again,as has always been the case with respect to the specification of apatent application, particular context of description and/or usageprovides helpful guidance regarding reasonable inferences to be drawn.

In the preceding description, various aspects of claimed subject matterhave been described. For purposes of explanation, specifics, such asamounts, systems, and/or configurations, as examples, were set forth. Inother instances, well-known features were omitted and/or simplified soas not to obscure claimed subject matter. While certain features havebeen illustrated and/or described herein, many modifications,substitutions, changes, and/or equivalents will occur to those skilledin the art. It is, therefore, to be understood that the appended claimsare intended to cover all modifications and/or changes as fall withinclaimed subject matter.

What is claimed is:
 1. An apparatus, comprising: a plurality ofindividually selectable memory devices, wherein at least a subset of theplurality of individually selectable memory devices individuallycomprise: a memory element, and a correlated electron material (CEM)device coupled in series with the memory element, wherein the CEM deviceto operate in a region of an impedance profile that is absent a Mott orMott-like transition at least during write operations for the memoryelement.
 2. The apparatus of claim 1, wherein a resistance of the memoryelement operates the CEM device in the region of the impedance profilethat is absent the Mott or Mott-like transition at least during thewrite operations for the memory element.
 3. The apparatus of claim 1,wherein the plurality of individually selectable memory devices arearranged in a cross-point array.
 4. The apparatus of claim 1, whereinone or more particular memory devices of the plurality of individuallyselectable memory devices are coupled between one or more particularelectrodes of a first metal layer and one or more particular electrodesof a second metal layer.
 5. The apparatus of claim 4, wherein the one ormore particular electrodes of the first metal layer to be electricallycoupled to individual memory elements of the one or more particularmemory devices of the plurality of individually selectable memorydevices, and wherein the one or more particular electrodes of the secondmetal layer to be electrically coupled to individual OEM devices of theone or more particular memory devices of the plurality of individuallyselectable memory devices.
 6. The apparatus of claim 5, wherein theindividual OEM devices of the one or more particular memory devices ofthe plurality of individually selectable memory devices to electricallycouple the individual memory elements of the one or more particularmemory devices of the plurality of individually selectable memorydevices between the one or more particular electrodes of the first metallayer and the one or more particular electrodes of the second metallayer during write operations directed to the one or more particularmemory devices.
 7. The apparatus of claim 5, wherein the one or moreparticular electrodes of the first metal layer comprise one or morewordlines and wherein the one or more particular electrodes of thesecond metal layer comprise one or more bitlines.
 8. The apparatus ofclaim 1, wherein the memory element to comprise a spin-transfer torquemagnetic memory element or a resistive memory element, or a combinationthereof.
 9. The apparatus of claim 8, wherein the resistive memoryelement to comprise a phase change memory element, a conductive bridgingmemory element or a nanotube memory element, or a combination thereof.10. A method, comprising: limiting a current flow through one or moreindividually selectable memory devices, the individually selectablememory devices individually comprising a memory element and a correlatedelectron material (OEM) device, to bring about write operations of thememory element absent a Mott or Mott-like transition in the OEM device.11. The method of claim 10, wherein the limiting the current flowthrough the one or more individually selectable memory devices compriseslimiting the current flow at least in part via a resistance of thememory element.
 12. The method of claim 10, wherein the one or moreindividually selectable memory devices are coupled between one or moreparticular electrodes of a first metal layer and one or more particularelectrodes of a second metal layer.
 13. The method of claim 12, whereinthe limiting the current flow through the one or more individuallyselectable memory devices comprises limiting a current flow between theone or more particular electrodes of the first metal layer and the oneor more particular electrodes of the second metal layer at least in partvia a current-limiting circuit.
 14. The method of claim 12, furthercomprising applying a particular voltage across the one or moreparticular electrodes of the first metal layer and one or moreparticular electrodes of the second metal layer as part of the writeoperations for the memory element.
 15. The method of claim 14, whereinthe one or more particular electrodes of the first metal layer tocomprise one or more wordlines and wherein the one or more particularelectrodes of the second metal layer comprise one or more bitlines. 16.The method of claim 10, wherein the memory element to comprise aspin-transfer torque magnetic memory element or a resistive memoryelement, or a combination thereof.
 17. The method of claim 16, whereinthe resistive memory element comprises a phase change memory element, aconductive bridging memory element or a nanotube memory element, or acombination thereof.
 18. The method of claim 10, wherein the one or moreindividually selectable memory devices are arranged in a cross-pointarray.
 19. An array of individually selectable memory devicesindividually comprising: a memory element; and a correlated electronmaterial (CEM) device coupled in series with the memory element, whereina resistance of the memory element to limit current to operate the CEMdevice absent a Mott or Mott-like transition during write operations forthe memory element.
 20. The array of individually selectable memorydevices of claim 19, wherein the memory element to comprise a resistivememory element or a magnetic memory element, or a combination thereof,and wherein the CEM device to operate as a diode-type device.